The present invention relates to pixel designs for solid state imagers. More specifically, the present invention relates to pixel designs having one or more access transistors and a photosensitive resistive load located above the access transistors.
CMOS image sensors are now becoming competitive with charge coupled device ("CCD") image sensors. Potential applications include digital cameras, night time driving displays for automobiles, and computer peripherals for document capture and visual communications.
Since the 1970s, CCD arrays have dominated the electronic image sensor market. They have outperformed CMOS array sensors in most important criteria including quantum efficiency, optical fill factor (the fraction of a pixel used for detection), charge transfer efficiency, readout rate, readout noise, and dynamic range. However, the steady improvement in CMOS technology (including increasingly small device size) has moved CMOS image sensors into a competitive posture. Further, in comparison to CCD technology, CMOS technology provides lower power consumption, increased functionality, and potentially lower cost. Researchers now envision single chip CMOS cameras having (a) integrated timing and control electronics, (b) a sensor array, (c) signal processing electronics, (d) an analog-to-digital converter, and (e) interface electronics. See Fossum, "CMOS Image Sensors: Electronic Camera On A Chip," IEDM Technical Digest, pp. 17-25, December 1995, which is incorporated herein by reference for all purposes.
CCD arrays are limited in that all image data is read by shifting analog charge packets from the CCD array interior to the periphery in a pixel-by-pixel manner. The pixels of the CCD array are not randomly addressable. In addition, due to voltage, capacitance, and process constraints, CCD arrays are not well suited to integration at the level possible in CMOS integrated circuits. Hence, any supplemental processing circuitry required for CCD sensors (e.g., memory for storing information related to the sensor) must generally be provided on separate chips. This, of course, increases the system's cost.
A conventional CMOS pixel, as illustrated in FIG. 1 (in top view) and described in the above-mentioned Fossum reference, includes one or two pass transistors 5 and 7 (shown as polysilicon gate strips) and a junction diode 11 (shown as a diffusion region in a semiconductor substrate). Regardless of how the signal is read (charge or voltage sensing, active or passive photodiode), the principle of a pixel's operation is based on the reverse biased junction capacitance modulation by light. Photons absorbed in the depletion region of the pre-charged (reverse biased) junction generate electron-hole pairs which discharge the capacitor. Larger junctions collect more photons and are more sensitive, but reduce the resolution of a sensor (as fewer pixels can be placed on available surface area). The lower limit of junction size is the diffraction limit of light.
As shown, access transistor(s) 5 and 7 and junction diode 11 are disposed side-by-side, essentially in the same plane, on the silicon substrate surface. Since the capacitance of the junction in a given technology can be easily set to a required value only by changing its dimensions, the pixel size is largely predetermined by the size of the junction. While the pixel size may be reduced slightly by making the access transistor(s) smaller, and thereby increasing the optical fill factor (the ratio of the pixel active area to the total pixel area), the transistors still limit the fill factor.
In the drive to further miniaturize electronic components including detectors/sensors, the current CMOS photodetector pixel design presents a significant limitation. What is needed therefore is an improved image sensor design that increases the optical fill factor of pixels in CMOS image arrays.